In my prior U.S. Pat. No. 4,288,872 I have disclosed such an equalizer, designed to enable transmission at speeds greater than twice Nyquist's rate, which includes linear and nonlinear filters for suppressing spurious oscillations of both the precursor and the postcursor type. Equalizers of the nonlinear kind compensating both precursor and postcursor effects are also the subject matter of my prior U.S. Pat. Nos. 4,170,758 and 4,283,788.
The equalizer particularly described and claimed in U.S. Pat. No. 4,288,872 comprises a first and a second circuit branch connected in parallel to the receiving end of a transmission path carrying a periodically sampled train of incoming digital signals or symbols. The first circuit branch includes a linear upstream filter for the partial suppression of postcursor effects, a first signal thus prefiltered being fed to a threshold-type decision stage and in parallel therewith to a delay line. The threshold circuit or decision stage emits a first quantized pulse to a nonlinear first downstream filter working into a first adder which also receives from the delay line the first prefiltered signal with a relative retardation of one sampling period. The first downstream filter emits a feed-forward signal serving to compensate precursor distortion in the delayed first prefiltered signal so that the first adder produces a first corrected signal which is at least partially purged of both precursor and postcursor interference.
The second circuit branch also includes a linear upstream filter which partially suppresses precursor effects and delivers a second prefiltered signal to a second adder provided with a feedback loop which includes another threshold-type decision stage followed by a second nonlinear downstream filter. The feedback signal derived by the last-mentioned filter from a quantized pulse emitted by the preceding threshold circuit or decision stage compensates postcursor distortion in the second prefiltered signal to generate a second corrected signal, at least partially purged from precursor and postcursor interference, in the output of the second adder. The two purged signals are fed to respective inputs of a third adder or summing circuit, with interposition of another delay line between the second and third adders in order to insure the temporal correlation of these two signals. A final decision stage converts the sum of the two purged signals into a quantized output pulse.
As further disclosed in U.S. Pat. No. 4,288,872, this quantized output pulse can be subjected to additional filtering and distortion compensation by algebraic summing to achieve a still higher degree of interference suppression.
The use of parallel circuit branches for precursor and postcursor correction reduces the probability of error propagation through feedback. Even if an error should develop in one branch, the summing of its output signal to that of the other branch minimizes its detrimental effect since the same error is unlikely to occur in both branches simultaneously. Still, the final decision stage downstream of the summing circuit lies effectively in cascade with an upstream threshold circuit in each branch so that its performance depends on the precision with which these two upstream stages operate. The threshold circuit of the second branch is particularly troublesome in this context since the feedback loop tends to intensify any decision error arising there.